DST1E1DK【PDF 1/4 页】KIT DESIGN SCT T1/E1 DS21X5Y

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Application Note 375

Interfacing User Devices and the

DST1E1DK SCT Design Kit

www.maxim-ic.com

DESCRIPTION

This application note is intended to show how to interface a user-defined device-under-test (DUT) or

development board with the DST1E1DK SCT Design Kit. The DST1E1DK development board was

single-chip transceivers (SCTs). These boards feature an 8051 processor-based microcontroller, on-board

EPROM, a socket for testing different Dallas Semiconductor SCTs, and a DS2172 Bit Error Rate Tester

(BERT). In addition to these features, the board offers a prototyping area and expansion ports. The focus

of this application note is to show how an expansion port can be used to expand the development board

functionality to include testing of user-defined devices or complete boards, giving the user virtually

unlimited testing flexibility.

EXPANSION PORT DEFINITION

There are two expansion ports labeled J7 and J10 on the DST1E1DK boards. The focus of this application

note will be J7. Expansion Port J7 provides user access to an 8-bit, microprocessor-multiplexed

address/data bus, four more most significant address bits, the Address Latch Enable (ALE), the

microprocessor read and write signals ( RD and WR , respectively), six different chip selects, and four

separate interrupts. Additionally, it provides access to the 5V, 3.3V, and ground planes. A pinout for

Expansion Port J7 is shown in Figure 1.

For most user applications, microprocessor bus access will be necessary. For instance, if the user wishes

to have read and write access to registers in the DUT or target board, that access is accomplished via this

bus. If separate address and data lines are needed, the multiplexed bus can be demultiplexed fairly easily

with the use of a latch, such as a 74HC373. A sample diagram is shown in Figure 2.

Once the address and data lines are demultiplexed, the user will have all signals necessary for a standard

processor interface, namely address, data, chip select, and read and write strobes. As is standard with Intel

based bus architectures, CS , RD , and WR strobes are active low. The 373 latch will serve to hold the

address lines stable when LE is low. For target reads, data can then be driven onto the bidirectional

address/data bus by the DUT as indicated by the RD pulse. For target writes, data will be driven onto the

address/data bus by the processor after the address bits have been latched via ALE, providing both stable

address and data at the time of the WR strobe. Please refer to the 8051-processor-family data sheets for

more detailed information regarding timing and bus characteristics.

The chip-select signals are generated by a standard 3-8 decoder on the DST1E1DK board using the upper

most address bits [14:12]. Chip Select 0 is used to access the SCT on the DST1E1DK board, while Chip

Select 1 is used to for accesses to the DS2172 BERT chip on the DST1E1DK board. The user can then

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